1. Field of the Invention
The present invention relates generally to semiconductor fabrication methods and, more particularly, to methods of transferring photolithographic patterns to a semiconductor substrate.
2. Description of Related Art
The density of memory chips continues to push technological limits as ever-greater numbers of memory cells are provided on a single chip. Memory chips are characterized by relatively large areas of nearly-identical devices, i.e., memory cells, the density of which often approaches limits dictated by photolithographic considerations. Methods have been and continue to be developed in the prior art by which large arrays of memory cells can be fabricated with relatively high density.
Memory chips frequently include, in addition to memory cells, electronic components such as select transistors, address decoders, drivers, and so on that do not exhibit the regularity of arrays of memory cells. These additional electronic components typically are placed in a peripheral area of the memory chip, separate from the memory array itself. As such, the additional electronic components tend to be more widely separated geometrically than do the components of memory cells. For this reason, seemingly identical structures as simple as connection paths, contact points, or holes, can, when fabricated by a process that includes photolithographic steps, appear different depending upon whether the structure appears in the array or in the peripheral area of a chip. For example, two parallel lines that represent conduction paths, when they appear very close together, may have their shape modified by an optical interference pattern that forms between the lines. By “close together” in this context it is meant that the distance between lines is on the order of the wavelength of the light used by the photolithographic process. Objects that appear in such close proximity can create optical interference effects not generated by more widely spaced objects. For this reason, identical features on a mask may not result in identical features on a chip after the features are transferred to the surface of a wafer.
FIG. 1A illustrates an example of a mask pattern that exhibits the effects just described. The pattern shown in FIG. 1A comprises a collection of relatively densely packed array features 100, having a square shape of length (S) on a side, located in an array region, and spaced according to an array pitch (PA) having a value on the order of the wavelength of the light used in the photolithographic process. Representative values of S are on the order of 0.16 μm; and typical values for PA may be about 0.3 μm. Often, S represents a critical dimension (CD), i.e., a dimension of a smallest possible feature that can be fabricated with a given manufacturing process. The CD represented by the features in FIG. 1A is the CD associated with the mask that defines features and may be referred to as a mask CD (MCD). Other forms of CD may correspond to a CD after a layer of photoresist exposed according to the mask pattern has been developed. Such a CD may be referred to as a development CD (DCD). After an etch step, the CD may be described as an etch CD (ECD).
The mask pattern illustrated in FIG. 1A further comprises a collection of peripheral features 200, which are not densely packed, the peripheral features 200 having a shape similar to the shape of the array features 100. The peripheral features 200 are located in a peripheral region and spaced according to a pitch (P1), where P1 is larger than PA. According to a representative numerical example, the value of the pitch P1 illustrated in FIG. 1A is about 1.5 μm. When the mask pattern illustrated in FIG. 1A is transferred to a wafer, optical interference effects can influence the size and shape of the closely spaced array features 100. However, the peripheral features 200 are not so affected because of their relatively wide spacing. Therefore, array features 100 and peripheral features 200 that appear to be identical (except for their spacing) on a mask will not always be identical when transferred to a wafer.
Typically, the effects of optical interference are factored into the design of a mask by adjusting the form of the array features 100 using methods known in the art. One view of this process is that the array features are “pre-distorted” so that the array features will appear as desired when they are transferred to a wafer. Optical interference effects, generally, have no effect on the peripheral features 200. Therefore, applying the same pre-distortion to the peripheral features 200 as is applied to the array features 100 results in the transfer of the peripheral features 200 to the wafer in a distorted form.
Methods are known that can compensate for the above-described effect of pre-distortion on peripheral elements. According to one example, a mask corresponding to a feature (e.g., a line, a hole, or a square as illustrated in FIG. 1A) in the peripheral area of a chip may have an added “assist feature” formed near the peripheral feature, the assist feature being designed to undo the effects of distortion on peripheral elements. Typically, the assist feature has a width narrow enough that the assist feature will not be transferred to the wafer by the photolithographic process (i.e., the assist feature will not “print out”). However, the assist feature can alter the phase of light waves near the peripheral feature, thereby causing the shape of the peripheral feature after transfer to a wafer to conform to the shape of an array feature.
FIG. 1B illustrates such a prior-art assist feature 205 added to the mask illustrated in FIG. 1A. The prior-art assist feature 205 has a fixed length S equal to the side dimension of the peripheral feature 200. The prior-art assist feature 205 further has a fixed width (wp) and is placed parallel to and separated from the peripheral feature 200 by a fixed distance (dp). For suitably chosen values of wp and dp, the pattern illustrated in FIG. 1B, when transferred to a wafer, prints out as the ideal mask illustrated in FIG. 1A as a consequence of adding the assist features 205.
Unfortunately, the method implicitly illustrated in FIG. 1B does not apply for all values of spacing between peripheral features 200. For example, as illustrated in FIG. 2, an application may place the same peripheral features 200 at a new spacing according to a pitch (P2) where P2 may range from about 0.6 μm to about 1 μm. In this range of spacing, the assist features 205 become closely enough spaced to create new optical interference effects. Accordingly, the peripheral features 200 may themselves become distorted when the mask pattern is transferred to a wafer. In practice, such distortion can occur for a certain range of pitch values that may be referred to as “forbidden pitch” values. These forbidden pitch values complicate the design of masks having array regions and peripheral regions. In particular, the allowable error in aligning masks of different layers of an integrated circuit can become unacceptably small, which condition can be described as a very small common window of usable photolithographic process parameters.
A need thus exists in the prior art for assist features that do not exhibit the forbidden pitch phenomenon. A further need exists for a method of placing assist features that leads to a relatively large common window of usable parameters of a photolithographic process.